1. Field of the Invention
The present invention relates to a semiconductor apparatus, and more particularly to the arrangement of circuits peripheral to a dynamic random access memory (DRAM).
2. Description of the Prior Art
Usually a semiconductor memory apparatus, such as a DRAM, consists of memory cell array forming sections, formed by arranging memory cells, and peripheral circuits adjacent to it, including sense amplifiers, row decoders and column decoders. Among these peripheral circuits, specific items such as sense amplifiers, one of which is provided for each pair of bit lines to each of which is supplied to a voltage in a complementary relationship to each one of a plurality of bit lines constituting the memory cell array, have to be installed at a rate of one unit per pair of bit lines. Therefore, these specific peripheral circuits are arranged along a side of said memory cell array forming sections.
In recent years, microprocessing techniques for semiconductors have made remarkable progress, resulting in a reduction in the area in which each bit of said memory cell is formed on a single semiconductor chip with a corresponding reduction in the pitch of the repetitive arrangement of each of bit line pairs connected to a plurality of said memory cells on said semiconductor chip.
Meanwhile, so-called specialized semiconductor memories embodying the application to functions unique to a particular system, typically including picture memories, have become commercially available and are extensively used. In such a specialized semiconductor memory, peripheral circuits for such system functions as serial data transfer and flash clear should be provided for each pair of said bit lines in order to realize these functions on said semiconductor chip. Thus, peripheral circuits used for said specialized semiconductor memory include line buffer circuits and serial switching circuits in addition to said sense amplifiers, resulting in a complex and large-scale configuration. Accordingly, it has become difficult to arrange these peripheral circuits along a side of said memory cell array forming sections at the repetitive pitch of said bit line pairs. Should said peripheral circuits be arranged in disregard of said repetitive pitch, the characteristics of transistors, which are the constituent elements of the peripheral circuits, would become unmatched, and moreover said bit line pairs would be laid in an elongated state, resulting in large resistances and capacities added to the bit line pairs.
This would have the consequence, as voltage variations on the bit line pairs are delayed when signals are read or written, of not only significantly slowing down the reading and writing rates of the semiconductor memory apparatus but also inviting erroneous operations.